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- VLSI D&T
- _VHDL CODE
- __AND Gate
- __OR Gate
- __NOT Gate
- __NAND Gate
- __NOR Gate
- __XNOR Gate
- __XOR Gate
- __Half Adder
- __Half Substractor
- __Full Adder
- __4Bit UP COUNTER
- __4Bit DOWN COUNTER
- __D Flip_Flop
- __SR Flip_Flop
- __JK Flip_Flop
- __T Flip_Flop
- _UNIT1
- __Syllabus
- __Introduction To VHDL
- __Language Elements
- __Operators
- _UNIT2
- __Clock Skew
- __Jitter
- __Clock Distribution
- __Power Distribution
- __Power Optimization
- __Interconnecting Routing
- _UNIT3
- AI
- _UNIT 1.FOUNDATION
- __Introduction To AI
- _UNIT 2:Searching
- _UNIT 3:Knowledge Representation
- IOT
- _UNIT 1:Fundamentals of IOT
- _UNIT 2:Sensors Networks
- _UNIT 3:Wireless Technologies for IOT
- _UNIT 4:IP Based protocols for IOT
- _UNIT 5:Data Handling & Analytics
- _UNIT 6:Applications of IOT
- CN&S
- _UNIT 1:Introduction to LAN(Local Area Network)
- _UNIT 2:Network Layer Part 1
- _UNIT 3:Network Layer Part 2
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UNIT 1.FOUNDATION
Introduction To AI
INTRODUCTION TO AI(Artificial Intelligence) Definition "a system's ability to correctly interpret external data, to learn from such data, …
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Interconnecting Routing QUE::Explain interconnecting routing technique. The basic objective of this design are area , delay, and power fl... -
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It is an electronic circuit having one or more than one input and only one output is based on certain logic.LOGICAL GATE are AND gate, OR ga...
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